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HEC4013BT-T NXP Semiconductors Dual D-type flip-flop ri Buy
N74F374D/G,118 NXP Semiconductors N74F374D - Octal D flip-flop (3-State) ri Buy
N74F74D/G,118 NXP Semiconductors N74F74D - Dual D-type flip-flop ri Buy

"Flip Flops"

Catalog Datasheet Results Type PDF Document Tags
Abstract: Function HD74 Series HD74S HD74S Series Dual 4-input Expanders 60 - • FLIP FLOPS Function HD74 Series HD74S HD74S Series J-K Master-Flip Flop (AND Inputs) 72 - Dual J-K Flip Flops 73 " - Dual D-type Edge-triggered Flip Flops 74 ^ 74 ' Dual J-K Flip Flops (with PR and CLR) 76 - Dual J-K Flip Flops 107 " - Dual J-K Negative-edge-triggered Flip Flops (with PR and CLR) - 112 - Dual J-K Negative-edge-triggered Flip Flops (with PR) - 113 Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR, and ... OCR Scan
datasheet

4 pages,
299.59 Kb

4-bit even parity checker 8 bit multiplier with shift register 8 bit ttl encoder DP-14 H183 HD74 hd74 series 4 inputs positive OR gates HD74S Synchronous 8-Bit Binary Counters synchronous binary counter with latch Flip flops datasheet abstract
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Abstract: 60 - • FLIP FLOPS Function HD74 Series HD74S HD74S Series J-K Master-Flip Flop (AND Inputs) 72 - Dual J-K Flip Flops 73 - - Dual D-type Edge-triggered Flip Flops 74 74 Dual J-K Flip Flops (with PR and CLR) 76 - Dual J-K Flip Flops 107 " - Dual J-K Negative-edge-triggered Flip Flops (wi th PR and CLR) - 112 - Dual J-K Negative-edge-triggered Flip Flops ( wi th PR) - 113 Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR, and Common CK) - 114 - Monostable Multivibrator 121 - - ... OCR Scan
datasheet

4 pages,
159.16 Kb

J-K latches 2 input nand gate 24v 4-bit shift register 74 194 74 series 7 segment decoders H183 HD74 4-bit even parity checker 74 series logic gates 16-LINE TO 4-LINE PRIORITY ENCODERS HD74/HD74S HD74/HD74S abstract
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Abstract: TTL INTEGRATED CIRCUITS DUAL JK MASTER/SLAVE FLIP FLOP GENERAL DESCRIPTION The flip flops described herein are TTI, (Transistor-Transistor Logic) dual ]K Master/Slave flip flops. Asynchrorous CLEAR inputs are provided on the flip flops The device is totally monolithic and designed for use in high speed control and counting applications, where economy is required, and multiple dala inputs are not requiret. These devices meet all of the electrical and mechanical requirements of the equivalent 74 device. ... OCR Scan
datasheet

1 pages,
60.54 Kb

7474 flip flop 7474 d flip D flip flop IC 7474 flip flops ic for jk flip flop IC 7474 flipflop master slave jk flip flop 7474 truth table 7474 D flip flop features of ic 7474 d flip flop 7474 ic 7474 jk flip flop ic pin IC 7474 datasheet abstract
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Abstract: Register (Nx8) FPGA Logic +- Input Registers Input Register Block (5 Flip/Flops) TDI , Register Block (2 Flip/Flops) Multipliers sysCLOCK PLLs for clock management. Up to 4 per device. TAG sysDSP Tri-State Register Block (2 Flip/Flops) FPGA Fabric JTAG and SPI Ports with ... Original
datasheet

4 pages,
1700.75 Kb

LFXP217 128 BIT spi FPGA aes ddr2 ram chip FPGA UART JTAG header 2 x 8 lfxp2 128 BIT spi FPGA LFXP2-5E-6TN144C Lattice LFXP2 DDR2 SSTL class I/ODDR/DDR27 TAG128AES I/ODDR/DDR27 abstract
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Abstract: 73 - - Dual D-tvpe Edge-triggercd Klip Flop« 74 ^ 74 Dual J-K Flip Flops (with FR and CI.RJ 76 Dual J-K Flip Flop* 107 /S Dual J-K Negiitivc-cd*e-triggered Flip Flops (with PR and CI.R) _ 112 - Dual J-K Ncgative-rdge-trigger«! Flip Flops (wich PR) - 113 DmI J-K Nefahte-edgr-tr^ered Flip Flops , Monnstable Muhivibrators 123 w - Hex D-type Flip Flops {with CI.R) 174 174 X Qua«!. D-type Flip Flop© Uith , Collector Output) - $5/ • EXPANDER Function HD74 Series I1D74S I1D74S Series Dual 4-input Expanders _ • FLIP ... OCR Scan
datasheet

4 pages,
139.51 Kb

HD74 H183 DP-14 74 series 7 segment decoders 2 input nand gate 24v 74 series logic gates HD74/HD74S HD74/HD74S abstract
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Abstract: Flip Flops with 3-State Outputs. 10-bit D-type Flip Flops with Dual Outputs. 10-bit Bus Interface Flip Flops , Registered Bus Transceivers with 3-State Outputs. 20-bit D-type Flip Flops with 3-State Outputs. 10-bit D-type Flip Flops with Dual Outputs. 10-bit Bus Interlace Flip Flops with 3-State Outputs. 18-bit ... OCR Scan
datasheet

4 pages,
225.28 Kb

HD74LVC/LV HD74ALVC/LVC/LV HD74ALVC HD74ALVCH16244 HD74ALVCH16245 HD74ALVCH16260 HD74ALVCH16269 HD74ALVCH16270 HD74ALVCH16373 HD74ALVCH16374 HD74ALVCH16500 HD74ALVCH16501 HD74ALVCH16543 HD74LVC/LV abstract
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Abstract: SN54ALS29825 SN54ALS29825, SN74ALS29825 SN74ALS29825, SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS , DALLAS. TEXAS 75265 SN54ALS29825 SN54ALS29825, SN74ALS29825 SN74ALS29825, SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE , INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS FUNCTION TABLE INPUTS OUTPUT OC* CLR CLKEN CLK D Q L L X X , SN54ALS29825 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS absolute maximum ratings over operating , TEXAS 75265 SN54ALS29825 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS switching ... OCR Scan
datasheet

8 pages,
466.81 Kb

SN74ALS29826 SN74ALS29825 SN54ALS29825 JD 1801 D2829 AM29825 1N916 1N3064 SN54ALS29825 abstract
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Abstract: s o n y ._CXB1541Q-Y CXB1541Q-Y Hex 2 : 1 Multiplexer with D-F.F. Description The C XB1541Q XB1541Q -Y is an ultra high speed monolithic ECL 1C, which contains six 2: 1 multiplexers foll owed by D type flip flops. The data select (SEL) input determines which data is enabled. The selected data is transferred to the flip flops output by the positive transition of clock (C1,C2) inputs. The Master Reset (MR) overrides all other control inputs and turns Q outputs to LOW. Featu res · Typical clock rate up to 2.3 GHz ... OCR Scan
datasheet

3 pages,
46.11 Kb

CXB1541Q-Y XB1541Q CXB1541Q-Y abstract
datasheet frame
Abstract: SONY. Hex 2 : 1 Multiplexer with D -FF Description The CXB1141Q CXB1141Q is an ultra high speed monolithic ECU 1C, which contains six 2: 1 multiplexers foll owed by D type flip flops. The data select (SEL) input determines which data is enabled. The selected data is transferred to the flip flops output by the positive transition of clock (C1,C2) inputs. The Master Reset (MR) overrides all other control inputs and turns Q outputs to LOW. CXB1141Q/Q-Y CXB1141Q/Q-Y Pin Assignment Features · Typical clock rate up to 2.6 GHz ... OCR Scan
datasheet

3 pages,
49.95 Kb

CXB1141Q CXB1141Q abstract
datasheet frame
Abstract: SONY» Quad 4 : 1 Multiplexer with D-F.F. Description The C X B 1 5 4 3 Q -Y is an ultra high speed monolithic E C L 1C, which contains four 4 : 1 multiplexers foll owed by 0 type flip flops. The data select (So, S i) inputs determine which data is enabled. The selected data is transferred to the flip flops output by the positive transition of clock (C) input The M aster Reset (M R ) overrides all other control inputs and turns Q outputs to LOW. CXB1543Q-Y CXB1543Q-Y Pin A ssignm ent nnnnnnnn 2 4 2 3 2 ... OCR Scan
datasheet

3 pages,
46.54 Kb

datasheet abstract
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Datasheet Content (non pdf)

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Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
>> Semiconductor Home > Products > D Type 3 State Flip Flops - Parametric Table devices: Table Data Updated on: 1/6/1999 (c) Copyright 1999 Texas Instruments Incorporated. All rights reserved. Trademarks , Important Notice! | Privacy Policy
www.datasheetarchive.com/files/texas-instruments/data/wwwti~1.com/sc/docs/psheets/parms/d_type~1.tpl
Texas Instruments 29/01/2000 4.86 Kb TPL d_type~1.tpl
>> Semiconductor Home > Products > D Type 3 State Flip Flops - Parametric Table devices: Table Data Updated on: 1/6/1999 (c) Copyright 1999 Texas Instruments Incorporated. All rights reserved. Trademarks , Important Notice! | Privacy Policy
www.datasheetarchive.com/files/texas-instruments/data/www.ti.com/sc/docs/psheets/parms/d_type_3_state_flip_flops.tpl
Texas Instruments 29/01/2000 4.86 Kb TPL d_type_3_state_flip_flops.tpl
2000. 4000, 5200 flip flops have? Record #151 Problem Title: XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200: What set, reset capabilities do the 2000. 4000, 5200 flip flops have? Problem Description: Keywords Solution 1: Due to architectural differences in the flip flops in the 2, 3, and 4k families of devices, the same set and reset abilities are not available to
www.datasheetarchive.com/files/xilinx/docs/wcd00002/wcd00216.htm
Xilinx 17/07/1998 3.83 Kb HTM wcd00216.htm
2000. 4000, 5200 flip flops have? Record #151 Problem Title: XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200: What set, reset capabilities do the 2000. 4000, 5200 flip flops have? Problem Description: Keywords Solution 1: Due to architectural differences in the flip flops in the 2, 3, and 4k families of devices, the same set and reset abilities are not available to
www.datasheetarchive.com/files/xilinx/docs/wcd00002/wcd00293-v1.htm
Xilinx 16/02/1999 3.92 Kb HTM wcd00293-v1.htm
syntax only looks at the rising or falling edge flip flops in that time group. The time group may only include the Flip Flops from that time group. The Problem is that the timing group contains the rising or falling edge flip flops, along with other synchronous elements (Rams, Latches) will be Solution 1: Create a time group of only flip flops. TIMEGROUP my_timing_grp_rising_FFS = RISING
www.datasheetarchive.com/files/xilinx/docs/rp00019/rp019ff.htm
Xilinx 29/02/2000 4.86 Kb HTM rp019ff.htm
capabilities do the 2000. 4000, 5200 flip flops have? Record #151 Problem Title: XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200 XC2000/XC3000/XC4000/XC5200: What set, reset capabilities do the 2000. 4000, 5200 flip flops have? Problem Description: Keywords Solution 1: Due to architectural differences in the flip flops in the 2, 3, and 4k families of devices, the same set and reset
www.datasheetarchive.com/files/xilinx/docs/rp0000c/rp00c33.htm
Xilinx 29/02/2000 4.67 Kb HTM rp00c33.htm
Answers Database Exemplar Spectrum 1998.2 is not inferring Xilinx Virtex flip flops with both synchronous set and reset Record Xilinx Virtex flip flops with both synchronous set and reset Problem Description: Urgency version contains fixes for inferring Xilinx Virtex flip flops with synchronous set or reset. Currently
www.datasheetarchive.com/files/xilinx/docs/rp0001b/rp01b68.htm
Xilinx 29/02/2000 5.08 Kb HTM rp01b68.htm
the Global Reset will not affect the flip flops using the local reset. These flip flops will lines: h GSRT sim l GSRT This will pulse the GSRT signal and reset all the flip flops. The GSR pin on all the flip flops will be defined and the simulation will proceed correctly. End of
www.datasheetarchive.com/files/xilinx/docs/wcd0000b/wcd00b57-v2.htm
Xilinx 04/06/1999 4.77 Kb HTM wcd00b57-v2.htm
Reset will not affect the flip flops using the local reset. These flip flops will produce an X on This will pulse the GSRT signal and reset all the flip flops. The GSR pin on all the flip flops will
www.datasheetarchive.com/files/xilinx/docs/rp00017/rp01733.htm
Xilinx 29/02/2000 5.41 Kb HTM rp01733.htm
report does not report this parameter. Itt only reports the number of LUTs, Flip Flops, Latches, and to the total number of flip flops and latches, a close enough approximation of the number of PACKED (4_Input_LUTs) / 2 Alternatively, if the total number of non-IOB latches and flip flops is greater than then total number of LUTs then use the following formula: Number of Packed CLBs = (Flip Flops + Latches
www.datasheetarchive.com/files/xilinx/docs/wcd00008/wcd00848-v1.htm
Xilinx 16/02/1999 4.16 Kb HTM wcd00848-v1.htm