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"Flip Flops"

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Abstract: Function H 1)7', Series HD74S HD74S Series Dual 4-input Expanders 60 — • FLIP FLOPS Function HD74 Series HD74S HD74S Series J-K Master-Flip Flop (AND Inputs) 72 — Dual J-K Flip Flops 73 - — Dual D-type Edge-triggered Flip Flops 74 74 Dual J-K Flip Flops (with PR and CLR) 76 — Dual J-K Flip Flops 107 " — Dual J-K Negative-edge-triggered Flip Flops (wi th PR and CLR) — 112 - Dual J-K Negative-edge-triggered Flip Flops ( wi th PR) — 113 Dual J-K Negative-edge-triggered Flip ... OCR Scan
datasheet

4 pages,
159.16 Kb

J-K latches H183 2 input nand gate 24v 74 series 7 segment decoders HD74 J-K Flip flops Flip Flops 4-bit shift register 74 194 4-bit even parity checker 74 series logic gates 16-LINE TO 4-LINE PRIORITY ENCODERS HD74/HD74S TEXT
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Abstract: HD74 Series HD74S HD74S Series Dual 4-input Expanders 60 — • FLIP FLOPS Function HD74 Series HD74S HD74S Series J-K Master-Flip Flop (AND Inputs) 72 — Dual J-K Flip Flops 73 " — Dual D-type Edge-triggered Flip Flops 74 ^ 74 ' Dual J-K Flip Flops (with PR and CLR) 76 — Dual J-K Flip Flops 107 " — Dual J-K Negative-edge-triggered Flip Flops (with PR and CLR) — 112 - Dual J-K Negative-edge-triggered Flip Flops (with PR) — 113 Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR ... OCR Scan
datasheet

4 pages,
299.59 Kb

H183 4-bit even parity checker 8 bit multiplier with shift register 8 bit ttl encoder hd74 series DP-14 4 inputs positive OR gates synchronous binary counter with latch HD74 HD74S Synchronous 8-Bit Binary Counters J-K Flip flops HD74/HD74S NAND Gates HD74/HD74S "J-K Flip flops" HD74/HD74S Flip flops HD74/HD74S 74 series logic gates HD74/HD74S 16-LINE TO 4-LINE PRIORITY ENCODERS HD74/HD74S HD74/HD74S HD74/HD74S TEXT
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Abstract: Dual 4-input Expanders _ • FLIP FLOPS Function HD74 Series IID74S IID74S Series J-K Master-Flip Flop , Dual J-K Flip Flops (with FR and CI.RJ 76 Dual J-K Flip Flop* 107 /S Dual J-K Negiitivc-cd*e-triggered Flip Flops (with PR and CI.R) _ 112 - Dual J-K Ncgative-rdge-trigger«! Flip Flops (wich PR) — 113 DmI J-K Nefahte-edgr-tr^ered Flip Flops (with PR. Common CLR. and CnDM CK) 1U - Monostable MuJtivibrator 121-^ Dual Retrifctferable Monnstable Muhivibrators 123 w — Hex D-type Flip Flops {with CI.R ... OCR Scan
datasheet

4 pages,
139.51 Kb

quad jk flip flop HD74 H183 DP-14 74 series 7 segment decoders 2 input nand gate 24v 74 series logic gates Flip Flops HD74/HD74S HD74S TEXT
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Abstract: TTL INTEGRATED CIRCUITS DUAL JK MASTER/SLAVE FLIP FLOP GENERAL DESCRIPTION The flip flops described herein are TTI, (Transistor-Transistor Logic) dual ]K Master/Slave flip flops. Asynchrorous CLEAR inputs are provided on the flip flops The device is totally monolithic and designed for use in high speed control and counting applications, where economy is required, and multiple dala inputs are not requiret , after clock pulse. DUAL D FLIP FLOP GENERAL DESCRIPTION The 7474 is designed for use where the ... OCR Scan
datasheet

1 pages,
60.54 Kb

D flip flop IC 7474 d flip ic for jk flip flop IC 7474 flipflop 7474 flip flops master slave jk flip flop 7474 flip flop features of ic 7474 d flip flop 7474 ic 7474 D flip flop 7474 truth table 7474 jk flip flop ic d flip flop 7474 pin IC 7474 7474 j-k flip flop features of ic 7474 ic 7474 JK flip flop IC T flip flop IC ic D flip flop 7474 TEXT
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Abstract: within the 6121 IOC. Each controller has a set of control and status flip flops which are defined below , to be programmed as discussed above. Also, all five flag flip flops are cleared as are the flag sample and interrupt sample flip flops. The interrupt enable flip flops are all set. The strobe flip , flag, flag sample, interrupt sample, interrupt inhibit and strobe flip flops are not disturbed by the , and strobe flip flops. It does not set up the IOC for programming, nor does it disturb the state of ... OCR Scan
datasheet

8 pages,
636.13 Kb

harris 6121 D flip flop IC 6121 harris 6121 T flip flop IC CMOS T flip flop IC no T flip flop IC HD-6121 TEXT
datasheet frame
Abstract: a set of control and status flip flops which are defined below: FLAG FLIP FLOP - Internal device , as discussed above. Also, all five flag flip flops are cleared as are the flag sample and interrupt samplef lip flops. The interrupt enable flip flops are all set. The strobe flip flops are cleared, the , , interrupt sample, interrupt inhibit and strobe flip flops are not disturbed by the programming function , met set their interrupt sample flip flops. Note that this is an edge triggered sef and is not a ... OCR Scan
datasheet

8 pages,
381.01 Kb

HD-6495 HD-6121 dx61 DX10 d flip flop T flip flop IC no flip flop T flip flop IC TEXT
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Abstract: MM74HCT08M MM74HCT08M Quad 2-Input AND Gate MM74HCT32M MM74HCT32M Quad 2-Input OR Gate MM74HCU04M MM74HCU04M Hex Inverter Flip Flops & , 0.38 0.48 0.45 1.63 1.63 1.63 0.30 0.34 0.34 0.35 0.30 0.30 Flip Flops & Registers 74ACT74SC 74ACT74SC Dual D , -Input OR Gate 74AC86SC 74AC86SC Quad 2-input Exclusive-OR Gate Flip Flops & Registers 74AC74SC 74AC74SC Dual D Flip-Flop , Trigger Input Flip Flops & Registers 74ACTQ273SC 74ACTQ273SC Octal D Flip-Flop with Clear 74ACTQ16374SSC 74ACTQ16374SSC 16-Bit D , -Input OR Gate 74VHC86M 74VHC86M Quad 2-Input Exclusive OR Gate Flip Flops & Registers 74VHC74M 74VHC74M Dual D Flip-Flop with ... Original
datasheet

3 pages,
57.24 Kb

74AC04SC 74ACT399SC MM74HC273WM cd4046bcm cd4052bcm CD4025BCM MM74HC00M MM74HC04M MM74HC125M MM74HC74AM MM74HC138M MM74HC14M octal Bilateral Switches MM74HC MM74HC MM74HC00M MM74HC02M MM74HC08M MM74HC32M MM74HC86M MM74HC132M MM74HC174M MM74HC175M MM74HC123AM MM74HC221AM MM74HC423AM MM74HC4538M MM74HCT/U TEXT
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Abstract: met, so the only roadblock is the clock to output time for the T flip flop. Toggle flip flops have , the logic attached to the input of the flip flops, with a single product term being needed for simple , the sum of products logic and simply show the overall result of tying consecutive flip flops together , attaching to the fast input sites on the entry flip flops. Note that each is clocked by the opposite phase , flip flops operating in the "dual edge triggered" mode. Note that the T flops are initialized out of ... Xilinx
Original
datasheet

9 pages,
65.48 Kb

XAPP379 CoolRunner-II CPLD flip flop T Toggle FLIP FLOP toggle COOLRUNNER-II XAPP375 XAPP377 XAPP378 XAPP376 verilog code for johnson counter COOLRUNNER-II 7 segment t flip flop TEXT
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Abstract:  SN54ALS29825 SN54ALS29825, SN74ALS29825 SN74ALS29825, SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS , 655012 • DALLAS. TEXAS 75265 SN54ALS29825 SN54ALS29825, SN74ALS29825 SN74ALS29825, SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS , €¢ DALLAS, TEXAS 75265 SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS FUNCTION TABLE , Instruments POST OFFICE BOX 656012 • DALLAS. TEXAS 75265 SN54ALS29825 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH , SN54ALS29825 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS switching characteristics PARAMETER FROM ... OCR Scan
datasheet

8 pages,
466.81 Kb

SN74ALS29826 1N3064 1N916 AM29825 D2829 JD 1801 SN54ALS29825 SN74ALS29825 Flip Flops AM29826 TEXT
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Abstract: requests are generated only when the sense flip flops are set by an edge and interrupts are enabled by writing to control reg A. Sense flip flops are reset on the following conditions. SENSE FLIP FLOPS , system performance. The PIE samples the sense flip flops and generates an interrupt request for enabled , the HM-6100 HM-6100 when sense flip flops are set during SKIP instructions. This output is open drain. 40 , information — not guaranteed. 5-32 Programmable Sense Inputs The sense inputs are used to set sense flip ... OCR Scan
datasheet

4 pages,
139.33 Kb

HM-6100 HD-6103 HD-6101C-9 HD-6101 dx 400 1500C TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
output flip flops (OFDT) via theTIMEGRP statement. Solutions Database TNM's cannot be attached to tri-stated output flip flops (OFDT) via theTIMEGRP statement. Product Family be attached to tri-stated output flip flops (OFDT) via the TIMEGRP statement. Problem Description: - When the TIMEGRP statement is used to tag a flip flop, the output netname of the flip flop is used to define the flip flop. Because of the fact that the OFD T component is actually a macro with an OFD
/datasheets/files/xilinx/weblinx/techdocs/800.htm
Xilinx 23/09/1996 1.99 Kb HTM 800.htm
New Technical Documents for D TYPE FLIP FLOPS New Technical Documents for D TYPE FLIP FLOPS Date Added Document Type Document Title Size (KB) New or Revised 12/04/98 DATA SHEET CD40175B CD40175B, CD40175B CD40175B TYPES , (Abstract) 243 New 12/04/98 DATA SHEET CD40174B CD40174B, CD40174B CD40174B TYPES , (Abstract) 215 New 12/04/98 DATA SHEET CD4013B CD4013B, CD4013B CD4013B TYPES , (Abstract) 217 New 12
/datasheets/files/texas-instruments/data/sc/docs/psheets/newdocs/logic19.htm
Texas Instruments 08/02/1999 7.79 Kb HTM logic19.htm
H Function Generators 0 196 0% CLB Flip Flops 8 392 2% IOB Input Flip Flops 0 112 0% IOB Output Flip Flops 8 112 7% 3-State Buffers
/datasheets/files/xilinx/bbs/swhlp/synopsys/vhdl/gsr/use_gsr.rpt
Xilinx 31/05/1995 7.73 Kb RPT use_gsr.rpt
H Function Generators 0 196 0% CLB Flip Flops 0 392 0% IOB Input Flip Flops 0 112 0% IOB Output Flip Flops 1 112 0% 3-State Buffers
/datasheets/files/xilinx/bbs/swhlp/synopsys/verilog/d_regist/d_regist.rpt
Xilinx 02/06/1995 7.59 Kb RPT d_regist.rpt
Merging of Flip Flops into IOB - logic. A total of 0 flip flops have been merged into io blocks. � X-BLOX for Design Signal Aliases . 5 Architectural Optimizations and Merging of Flip Flops into IOB . 6 Module Synthesis and Module Generation . 7 primitives 17 mapping primitives 16 flip flop primitives 39 logic primitives * RPM
/datasheets/files/xilinx/bbs/swhlp/synopsys/verilog/xbloxgen/alu.blx
Xilinx 05/06/1995 3.94 Kb BLX alu.blx
Period Constraints Period Constraints PERIOD PERIOD is the duration of the clock and can be configured to have different duty cycles Derived clocks can be defined as a function of another clock (*,/) PERIOD is preferred over FROM:TO constraints; The tools will have a faster runtime. PERIOD should cover most of design. Period only covers from Sync. Elements to other Sync. Elements, like Flip flops to flip flops
/datasheets/files/xilinx/docs/rp0006b/rp06bab.htm
Xilinx 29/02/2000 1.55 Kb HTM rp06bab.htm
D Type 3 State Flip Flops - Parametric Table >> Semiconductor Home > Products > D Type 3 State Flip Flops - Parametric Table devices: Table Data Updated on: 1/6/1999 (c) Copyright 1999 Texas Instruments Incorporated. All rights reserved. Trademarks , Important Notice! | Privacy Policy
/datasheets/files/texas-instruments/data/wwwti~1.com/sc/docs/psheets/parms/d_type~1.tpl
Texas Instruments 29/01/2000 4.86 Kb TPL d_type~1.tpl
H Function Generators 1 196 0% CLB Flip Flops 7 392 1% IOB Input Flip Flops 0 112 0% IOB Output Flip Flops 0 112 0% 3-State Buffers
/datasheets/files/xilinx/bbs/swhlp/synopsys/vhdl/state_ma/enum.rpt
Xilinx 01/06/1995 9.56 Kb RPT enum.rpt
H Function Generators 0 196 0% CLB Flip Flops 4 392 1% IOB Input Flip Flops 0 112 0% IOB Output Flip Flops 0 112 0% 3-State Buffers
/datasheets/files/xilinx/bbs/swhlp/synopsys/vhdl/rpm_exam/rpm_exam.rpt
Xilinx 31/05/1995 11.27 Kb RPT rpm_exam.rpt
H Function Generators 0 196 0% CLB Flip Flops 0 392 0% IOB Input Flip Flops 0 112 0% IOB Output Flip Flops 0 112 0% 3-State Buffers
/datasheets/files/xilinx/bbs/swhlp/synopsys/vhdl/res_shar/res_xbl0.rpt
Xilinx 31/05/1995 11.25 Kb RPT res_xbl0.rpt