NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| SN74F174ANSR | Texas Instruments | IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16, FF/Latch | 
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| SN74S112ANSRG4 | Texas Instruments | IC S SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16, FF/Latch |
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| CD54HC165M96 | Texas Instruments | IC HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, MS-012AC, SOIC-16, Shift Register |
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| SN74ALS323DW | Texas Instruments | IC ALS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, PLASTIC, SO-20, Shift Register |
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| 74LVC1G175GS,132 | NXP Semiconductors | Single D-type flip-flop with reset; positive edge trigger, SOT1202 Package |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Function HD74 Series HD74S HD74S Series Dual 4-input Expanders 60 - • FLIP FLOPS Function HD74 Series HD74S HD74S Series J-K Master-Flip Flop (AND Inputs) 72 - Dual J-K Flip Flops 73 " - Dual D-type Edge-triggered Flip Flops 74 ^ 74 ' Dual J-K Flip Flops (with PR and CLR) 76 - Dual J-K Flip Flops 107 " - Dual J-K Negative-edge-triggered Flip Flops (with PR and CLR) - 112 - Dual J-K Negative-edge-triggered Flip Flops (with PR) - 113 Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR, and ... | OCR Scan |
4 pages, |
DP-14 HD74 H183 4-bit even parity checker 8 bit ttl encoder 4 inputs positive OR gates Synchronous 8-Bit Binary Counters Flip flops "J-K Flip flops" 74 series logic gates 16-LINE TO 4-LINE PRIORITY ENCODERS HD74/HD74S HD74S HD74/HD74S abstract |
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| Abstract: 60 - • FLIP FLOPS Function HD74 Series HD74S HD74S Series J-K Master-Flip Flop (AND Inputs) 72 - Dual J-K Flip Flops 73 - - Dual D-type Edge-triggered Flip Flops 74 74 Dual J-K Flip Flops (with PR and CLR) 76 - Dual J-K Flip Flops 107 " - Dual J-K Negative-edge-triggered Flip Flops (wi th PR and CLR) - 112 - Dual J-K Negative-edge-triggered Flip Flops ( wi th PR) - 113 Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR, and Common CK) - 114 - Monostable Multivibrator 121 - - ... | OCR Scan |
4 pages, |
HD74 H183 74 series 7 segment decoders 2 input nand gate 24v 4-bit even parity checker 74 series logic gates 16-LINE TO 4-LINE PRIORITY ENCODERS HD74/HD74S HD74S HD74/HD74S abstract |
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| Abstract: TTL INTEGRATED CIRCUITS DUAL JK MASTER/SLAVE FLIP FLOP GENERAL DESCRIPTION The flip flops described herein are TTI, (Transistor-Transistor Logic) dual ]K Master/Slave flip flops. Asynchrorous CLEAR inputs are provided on the flip flops The device is totally monolithic and designed for use in high speed control and counting applications, where economy is required, and multiple dala inputs are not requiret. These devices meet all of the electrical and mechanical requirements of the equivalent 74 device. ... | OCR Scan |
1 pages, |
7474 d-flip flop 7474 flip flop 7474 d flip 7474 flip flops ic for jk flip flop IC 7474 flipflop 7474 truth table 7474 jk flip flop ic master slave jk flip flop 7474 D flip flop features of ic 7474 d flip flop 7474 ic datasheet abstract |
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| Abstract: Register (Nx8) FPGA Logic +- Input Registers Input Register Block (5 Flip/Flops) TDI , Register Block (2 Flip/Flops) Multipliers sysCLOCK PLLs for clock management. Up to 4 per device. TAG sysDSP Tri-State Register Block (2 Flip/Flops) FPGA Fabric JTAG and SPI Ports with ... | Original |
4 pages, |
FPGA UART ddr2 ram chip 128 BIT spi FPGA aes 128 BIT spi FPGA LFXP2-5E-6TN144C Lattice LFXP2 DDR2 SSTL class I/ODDR/DDR27 TAG128AES I/ODDR/DDR27 abstract |
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| Abstract: Series I1D74S I1D74S Series Dual 4-input Expanders _ • FLIP FLOPS Function HD74 Series IID74S IID74S Series J-K , Dual J-K Flip Flops (with FR and CI.RJ 76 Dual J-K Flip Flop* 107 /S Dual J-K Negiitivc-cd*e-triggered Flip Flops (with PR and CI.R) _ 112 - Dual J-K Ncgative-rdge-trigger«! Flip Flops (wich PR) - 113 DmI J-K Nefahte-edgr-tr^ered Flip Flops (with PR. Common CLR. and CnDM CK) 1U - Monostable MuJtivibrator 121-^ Dual Retrifctferable Monnstable Muhivibrators 123 w - Hex D-type Flip Flops {with CI.R) 174 ... | OCR Scan |
4 pages, |
FLIP FLOP RS 2 input nand gate 24v 4-bit even parity checker HD74/HD74S HD74S HD74/HD74S abstract |
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| Abstract: 73 - - Dual D-tvpe Edge-triggercd Klip Flop« 74 ^ 74 Dual J-K Flip Flops (with FR and CI.RJ 76 Dual J-K Flip Flop* 107 /S Dual J-K Negiitivc-cd*e-triggered Flip Flops (with PR and CI.R) _ 112 - Dual J-K Ncgative-rdge-trigger«! Flip Flops (wich PR) - 113 DmI J-K Nefahte-edgr-tr^ered Flip Flops , Monnstable Muhivibrators 123 w - Hex D-type Flip Flops {with CI.R) 174 174 X Qua«!. D-type Flip Flop© Uith , Collector Output) - $5/ • EXPANDER Function HD74 Series I1D74S I1D74S Series Dual 4-input Expanders _ • FLIP ... | OCR Scan |
4 pages, |
HD74 H183 DP-14 74 series 7 segment decoders 2 input nand gate 24v 74 series logic gates HD74/HD74S HD74S HD74/HD74S abstract |
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| Abstract: SN54ALS29825 SN54ALS29825, SN74ALS29825 SN74ALS29825, SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS , DALLAS. TEXAS 75265 SN54ALS29825 SN54ALS29825, SN74ALS29825 SN74ALS29825, SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE , INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS FUNCTION TABLE INPUTS OUTPUT OC* CLR CLKEN CLK D Q L L X X , SN54ALS29825 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS absolute maximum ratings over operating , TEXAS 75265 SN54ALS29825 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS switching ... | OCR Scan |
8 pages, |
SN74ALS29826 SN74ALS29825 SN54ALS29825 JD 1801 D2829 AM29825 1N916 1N3064 AM29826 SN54ALS29825 abstract |
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| Abstract: 74C76 74C76 flip flops also include preset inputs and are supplied in 16 pin packages. These flip flops are ... | OCR Scan |
1 pages, |
74C76 pin diagram 74C76 Flip flop JK cmos flip-flop 74c74 74C74 74C74 abstract |
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| Abstract: 29 72 21 D Flip Flops 28 28 28 28 28 72 32 8 10 10 10 10 76 12 JK Flip Flops 17 17 17 17 17 8 8 Toggle Flip Flops 18 18 , S-R Latches Scannable Flip Flops I/O1 Input Buffers Input Buffers with Pull Up/Pull Down I/O ... | Original |
6 pages, |
MSM98S MSM98Q MSM13Q 64512 44k1 J2N00153882 J2N00153882 abstract |
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| Abstract: Facts Core Specifics 720i/p Virtex-5 5083 Slice Flip Flops 10258 Slice LUTS 8 RAMB18x2, 20 RAMB36 RAMB36 ITU-R-BT.601 5072 Slice Flip Flops 10270 Slice LUTS 8 RAMB18x2, 16 RAMB36 RAMB36 CIF 5022 Slice Flip Flops 10240 Slice LUTS 8 RAMB18x2, 14 RAMB36 RAMB36 Xilinx ISETM 8.2.03i (from ngd_build , , Virtex-4, SpartanTM-3 5083 Slice Flip Flops 10258 Slice LUTS 8 RAMB18x2, 20 RAMB36 RAMB36 Synplicity ... | Original |
3 pages, |
H.264 microsoft 8627 1080p field pattern fpga 7831 RAMB36 H.264 integer transform DS602 DS602 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| Product listing for J-K type flip-flops Products listing -triggered flip-flops 74F112 74F112 74F112 74F112 - Dual J-K negative edge-triggered flip-flop 74F113 74F113 74F113 74F113 - Dual J-K negative edge-triggered flip-flops without reset 74F50109 74F50109 74F50109 74F50109 - Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune www.datasheetarchive.com/files/philips/catalog/listing/40695.html |
Philips | 25/04/2003 | 7.33 Kb | HTML | 40695.html |
| -triggered flip-flops 74F112 74F112 74F112 74F112 - Dual J-K negative edge-triggered flip-flop 74F113 74F113 74F113 74F113 - Dual J-K negative edge-triggered flip-flops without reset 74F50109 74F50109 74F50109 74F50109 - Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics 74HC107 74HC107 74HC107 74HC107 - Dual JK flip-flop with reset; negative-edge trigger 74HC109 74HC109 74HC109 74HC109 - Dual JK flip-flop with set and reset; positive-edge trigger 74HC112 74HC112 74HC112 74HC112 - dual JK flip-flop with set and reset; negative-edge trigger 74HC www.datasheetarchive.com/files/philips/catalog/listing/40695-v1.html |
Philips | 17/02/2002 | 5.98 Kb | HTML | 40695-v1.html |
| Product listing for J-K type flip-flops Products listing -triggered flip-flops 74F112 74F112 74F112 74F112 - Dual J-K negative edge-triggered flip-flop 74F113 74F113 74F113 74F113 - Dual J-K negative edge-triggered flip-flops without reset 74HC107 74HC107 74HC107 74HC107 - Dual JK flip-flop with reset; negative-edge trigger www.datasheetarchive.com/files/philips/catalog/listing/40695-v2.html |
Philips | 01/06/2005 | 5.93 Kb | HTML | 40695-v2.html |
| Spartan and XC4000 XC4000 XC4000 XC4000 Flip-flop Initialization Spartan and XC4000 XC4000 XC4000 XC4000 Flip-flop Initialization The following subsections describe IOB and CLB flip-flop initialization. IOB Flip-flop Initialization To set the initial value of Spartan/XL and XC4000E/L/EX/XV/XL XC4000E/L/EX/XV/XL XC4000E/L/EX/XV/XL XC4000E/L/EX/XV/XL IOB flip-flops at power-up, follow these instructions. Set the IOB flip-flops to power up either High or Low by attaching the appropriate INIT property (INIT=1 or INIT=0) to each IOB flip-flop in your www.datasheetarchive.com/files/xilinx/docsan/cad/cad7_4.htm |
Xilinx | 12/11/1998 | 2.04 Kb | HTM | cad7_4.htm |
| XC9500 XC9500 XC9500 XC9500 Flip-flop Initialization XC9500 XC9500 XC9500 XC9500 Flip-flop Initialization The following subsections describe XC9500 XC9500 XC9500 XC9500 flip-flop initialization. IOB Flip-flop Initialization XC9500 XC9500 XC9500 XC9500 devices do not contain IOB flip-flops. Macrocell Flip-flop Initialization To set the initial value of XC9500 XC9500 XC9500 XC9500 macrocell flip-flops at power-up in your simulation, follow these instructions flip-flops High or Low in your test fixture file. For timing simulation, set the macrocell flip-flops www.datasheetarchive.com/files/xilinx/docsan/cad/cad7_5.htm |
Xilinx | 12/11/1998 | 1.82 Kb | HTM | cad7_5.htm |
| Translating Flip-flops Chapter 8 Translating Flip-flops -instantiated flip-flops. It explains how to translate these flip-flops to always blocks that can be used with the benefits of translating your hand-instantiated flip-flops to always blocks are listed below flip-flop instantiations. There are three basic steps to translating a flip-flop to the always syntax. Understand the function of the module. Determine what parts of the module description provide the flip-flop www.datasheetarchive.com/files/xilinx/docsan/ver/ver8.htm |
Xilinx | 12/11/1998 | 2.32 Kb | HTM | ver8.htm |
| Xilinx Answer #584 : PPR 5.x guide may leave clock enable on flip-flops where CE was Banner -> Answers Database PPR 5.x guide may leave clock enable on flip-flops where CE was leave clock enable on flip-flops where CE was removed (3000A) Problem Description guide may leave clock enable on flip-flops where CE was removed (3000A) LONG DESCRIPTION: PROBLEM: A flip-flop has its clock enable removed in a 3000A design. The design is run through PPR using www.datasheetarchive.com/files/xilinx/docs/wcd00003/wcd00375-v1.htm |
Xilinx | 16/02/1999 | 4.47 Kb | HTM | wcd00375-v1.htm |
| Xilinx Answer #584 : PPR 5.x guide may leave clock enable on flip-flops where CE was removed !!! -> Answers Database PPR 5.x guide may leave clock enable on flip-flops 5.x guide may leave clock enable on flip-flops where CE was removed (3000A) Problem SHORT DESCRIPTION: PPR 5.x guide may leave clock enable on flip-flops where CE was removed (3000A) LONG DESCRIPTION: PROBLEM: A flip-flop has its clock enable removed in a 3000A design. The www.datasheetarchive.com/files/xilinx/docs/rp0000d/rp00d55.htm |
Xilinx | 29/02/2000 | 4.96 Kb | HTM | rp00d55.htm |
| Xilinx Answer #584 : PPR 5.x guide may leave clock enable on flip-flops where CE was Banner -> Answers Database PPR 5.x guide may leave clock enable on flip-flops where CE was leave clock enable on flip-flops where CE was removed (3000A) Problem Description guide may leave clock enable on flip-flops where CE was removed (3000A) LONG DESCRIPTION: PROBLEM: A flip-flop has its clock enable removed in a 3000A design. The design is run through PPR using www.datasheetarchive.com/files/xilinx/docs/wcd00002/wcd002fb.htm |
Xilinx | 17/07/1998 | 4.38 Kb | HTM | wcd002fb.htm |
| ST | HEX D-TYPE FLIP FLOP WITH CLEAR Datasheet HEX D-TYPE FLIP FLOP WITH CLEAR 74VHCT174A 74VHCT174A 74VHCT174A 74VHCT174A Document Format Size Document Number Date Update Pages Portable Document Format 7071 03/04/2000 10 Raw Text Format www.datasheetarchive.com/files/stmicroelectronics/books/all/7071.htm |
STMicroelectronics | 25/05/2000 | 2.68 Kb | HTM | 7071.htm |