Fulltext Datasheet Results		1 - 50 of about 10000+ for "AND Gate"
	First line: "AND Gate" NC7S08M5X NC7S08 TinyLogic® 2-Input Gate NC7S08 TinyLogic® 2-Input Gate Abstract: .. HS 2-Input AND Gate. �1995 Fairchild Semiconductor Corporation www.fairchildsemi.com. NC7S08 NC7S08 Rev. 1.9.0. March 2008. NC7S08 NC7S08 TinyLogic. �. HS 2-Input AND Gate. Features. ■. Space saving SOT23 SOT23 or SC70 SC70 ..  Tags: "AND Gate" SOT23-5 Fairchild  NC7S08M5X  NC7S08   NC7S08	456.14 Kb	11 Pages	Original
	First line: NC7SV08 TinyLogic® ULP-A 2-Input Gate NC7SV08 TinyLogic® ULP-A 2-Input Gate Abstract: .. ULP-A 2-Input AND Gate. NC7SV08 NC7SV08 TinyLogic � ULP-A 2-Input AND Gate. Features. É 0.9V to 3.6V VCC Supply Operation É 3.6V Over-Voltage Tolerant I/Os at VCC from 0.9V to 3.6V. É Extremely High Speed tPD ..  Tags:   NC7SV08	355.98 Kb	11 Pages	Original
	First line: "AND Gate" Appendix QDIF File Format Appendix QDIF File Format QuickLogic Data Interchange Format (QDIF) been fully specified implemented. QDIF provides open access framework SpDE additional user third-party tools. SpDE single ASCII file format which serves read write interface other systems. While Abstract: .. For example, if a 2 input AND gate is used in several places in the user's design, the implementation of an and gate in the pASIC macro cell is described here once. 2. Logical section—the logical ..  Tags: "AND Gate"   datasheet abstract..	938.17 Kb	4 Pages	Original
	First line: Fast Zero Power Traditional CPLDs CPLDs migrated from Bipolar CMOS Easier platform design upon Lower power consumption Continued same Bipolar design technique implement Product Terms Abstract: .. 8 - Input AND gate. Tpd < 0.5nsTpd < 0.6ns. Tpd < 0.8ns • Virtual mux controls input DeMorgan Tree generates logic Y = I. 0 I 1I 2I 3 = ! ! I 0 I 1 # ! I 2. I 3 Distributes capacitance Instantaneous Idd low ..  Tags:   datasheet abstract..	176.24 Kb	9 Pages	Original
	First line: 7Z08* NC7SZ08 TinyLogic® Two-Input Gate 2009 NC7SZ08 TinyLogic® Two-Input Gate Abstract: .. UHS Two-Input AND Gate. NC7SZ08 NC7SZ08 TinyLogic � UHS Two-Input AND Gate. Features. É Ultra-High Speed: tPD 2.7ns Typical into 50pF 50pF at 5V VCC É High Output Drive: �24mA 24mA at 3V VCC É Broad VCC Operating Range ..  Tags: 7Z08* NC7SZ08P5X*   NC7SZ08	523.42 Kb	10 Pages	Original
	First line: 74ls10 IC 74LS14N 74ls02n 74LS04N* 74ls04n Standard Logic Thousands pipeline addition shown below. Call save 10-20%. SOIC Series (Continued) General purpose family high speed advanced bipolar logic Save When Purchasing Texas Instruments Products. Abstract: .. 74LS08 74LS08 SOIC-14 SOIC-14 Quad 2-input AND gate 308654CJ 308654CJ SN74LS08D SN74LS08D .. .45 .364 .276. 74LS08 74LS08 DIP-14 DIP-14 Quad 2-input AND gate 295401CJ 295401CJ SN74LS08N SN74LS08N .. .45 .364 .276. 74LS09 74LS09 ..  Tags: 74ls04n 74LS04N* 74ls02n 74LS14N 74ls10 IC SN74LS11N  SN74LS07N  SN74LS05N  SN74F574N motorola  SN74F541N  signetics 74ls04  ON SEMI cross  octal counter application  not 74Ls08  not 74Ls05  MR301-24   datasheet abstract..	33.74 Kb	1 Pages	Original
	First line: LFSR COUNTER� LFSR COUNTER LFSR 8 bit LFSR Efficient Shift Registers, LFSR Counters, Long PseudoRandom Sequence Generators Application Note Peter Alfke Abstract: .. To divide by a number smaller than 15, use AND gate “C” in Figure 1 to decode the binary pattern listed in Table 1 next to the desired number. For ÷ 15 and any number listed to. the right of the & symbol ..  Tags: 8 bit LFSR LFSR COUNTER LFSR COUNTERÂ X5802*  mod 16 counter  LFSR   datasheet abstract..	58.02 Kb	6 Pages	Original
	First line: View from Programmable Logic Next Millenium expect that within first years next millennium will programmable logic devices inside every piece electronic equipment, because hardware will become just programmable software. Abstract: .. substantial increases in the cost of ownership for standard cell and gate-array technology. FPGAs eliminate the need for expensive NRE Non Recurring Engineering , development, system integration ..  Tags: Gate Array   datasheet abstract..	110.95 Kb	1 Pages	Original
	First line: lvc08a� LVC08A IDT74LVC08A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE WITH VOLT TOLERANT Abstract: .. IDT74LVC08A IDT74LVC08A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE. APRIL 1999. 1999 Integrated Device Technology, Inc. DSC-4585 DSC-4585 /- c. IDT74LVC08A IDT74LVC08A ADVANCE INFORMATION. EXTENDED COMMERCIAL TEMPERATURE ..  Tags: LVC08A lvc08a C 4585   IDT74LVC08A	92.12 Kb	5 Pages	Original
	First line: IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE Abstract: .. IDT74ALVC08 IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE. DESCRIPTION: MARCH 1999. 1999 Integrated Device Technology, Inc. DSC-4633 DSC-4633 /- c. IDT74ALVC08 IDT74ALVC08 ADVANCE INFORMATION. EXTENDED COMMERCIAL ..  Tags:   IDT74ALVC08	91.81 Kb	5 Pages	Original
	First line: IDT74ALVC1G08 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE 3.3V CMOS SINGLE 2-INPUT POSITIVEAND GATE IDT74ALVC1G08 ADVANCE INFORMATION Abstract: .. IDT74ALVC1G08 IDT74ALVC1G08 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE. GND. 2. 3 4. 5 1. B. VCC A. Y. SO5-1. MARCH 1999. 1999 Integrated Device Technology, Inc. DSC-4529 DSC-4529 /- c. IDT74ALVC1G08 IDT74ALVC1G08 ADVANCE INFORMATION. EXTENDED ..  Tags:   IDT74ALVC1G08	104.38 Kb	6 Pages	Original
	First line: NC7SVL08 TinyLogic® Low-ICCT Two-Input Gate 2009 NC7SVL08 TinyLogic® Low-ICCT Two-Input Gate Abstract: .. Two-Input AND Gate. NC7SVL08 NC7SVL08 TinyLogic � Low-ICCT Two-Input AND Gate Features. É 0.9V to 3.6V VCC Supply Operation É 3.6V Over-Voltage Tolerant I/Os at VCC from 0.9V to 3.6V. É Power-Off High-Impedance ..  Tags:   NC7SVL08	398.86 Kb	9 Pages	Original
	First line: NC7SP08 TinyLogic® Two-Input Gate 2009 NC7SP08 TinyLogic® Two-Input Gate Abstract: .. ULP Two-Input AND Gate. NC7SP08 NC7SP08 — TinyLogic � ULP Two-Input AND Gate. Features. É 0.9V to 3.6V VCC Supply Operation É 3.6V Over-Voltage Tolerant I/Os at VCC from 0.9V to 3.6V. É Propagation Delay tPD ..  Tags:   NC7SP08	413.6 Kb	9 Pages	Original
	First line: and logic gate pdf Gate Array Design Atmel flexible design approach allows customer develop database compatible with design flow through number different design methodologies. traditional design approach involves capturing schematic running logic simulation using Atmel macrocell library workstation Abstract: .. errors and potential problems, as well as calculate power and gate count. Incorporated in v3 is our Slew Rate Delay Calculator SRDC . The SRDC provides an interface with the simulators for very ..  Tags: and logic gate pdf   datasheet abstract..	5.38 Kb	1 Pages	Original
	First line: Plastic Packages Integrated Circuits Small Outline Exposed Plastic Packages (EPSOIC) SYMBOL 0.070 0.002 0.014 0.007 0.202 0.300 0.202 Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.25mm 25mm /.010" per side. 4. The configuration of Pin 1 is optional, but must be located within the zone indicated. ..  Tags:   datasheet abstract..	42.97 Kb	1 Pages	Original
	First line: GLASS-METAL SEAL FLAG TERMINAL (0.43) DIA. (0.26) (0.51) (0.71) (2.75) MAX. (0.06) DIA. Abstract: .. 2 = Flag terminals For Cathode and Gate Terminals 3 - Thyristor. 4 - Voltage code: Code x 10 = VRRM See Voltage Rating Table 5 - None = Stud base UNF 3/4 - 16UNF 16UNF threads. 6 - Critical dv/dt: None = 500V 500V ..  Tags: TO-93   datasheet abstract..	13.28 Kb	1 Pages	Original
	First line: MM74HCT08 Quad 2-Input Gate MM74HCT08 Quad 2-Input Gate Abstract: .. MM74HCT08 MM74HCT08 — Quad 2-Input AND Gate. �1983 Fairchild Semiconductor Corporation www.fairchildsemi.com. MM74HCT08 MM74HCT08 Rev. 1.3.0. March 2008. MM74HCT08 MM74HCT08 Quad 2-Input AND Gate. Features. ■. TTL, LS pin-out ..  Tags:   MM74HCT08	309.24 Kb	9 Pages	Original
	First line: jedec MO-150 "AND Gate" 74HC21 Dual 4-input gate Rev. November 2004 Product data sheet Abstract: .. 74HC21 74HC21 Dual 4-input AND gate Rev. 03 — 12 November 2004 Product data sheet. Table 1: Quick reference data GND = 0 V; Tamb = 25 �C; tr = t f = 6 ns. Symbol Parameter Conditions Min Typ Max Unit. tPHL, tPLH ..  Tags: "AND Gate" jedec MO-150 SO14 data sheet  74hc21   74HC21	71.72 Kb	15 Pages	Original
	First line: SN74AHCT1G08 SINGLE 2-INPUT POSITIVE-AND GATE SCLS315B MARCH 1996 REVISED NOVEMBER 1996 Inputs TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process High Latch-Up Immunity Exceeds JEDEC Standard JESD-17 Packaged Plastic Small-Outline Transistor Package Abstract: .. SINGLE 2-INPUT POSITIVE-AND GATE. SCLS315B SCLS315B ‐ MARCH 1996 ‐ REVISED NOVEMBER 1996. 1 POST OFFICE BOX 655303 ∞ DALLAS, TEXAS 75265. Inputs Are TTL-Voltage Compatible EPICΕ Enhanced-Performance ..  Tags:   SN74AHCT1G08	77.05 Kb	4 Pages	Original
	First line: and logic gate pdf Appendix QDIF File Format Appendix QDIF File Format QuickLogic Data Interchange Format (QDIF) been fully specified implemented. QDIF provides open access framework SpDE additional user third-party tools SpDE single ASCII file format which serves read write interface other systems Abstract: .. For example, if a 2 input AND gate is used in several places in the user's design, the implementation of an and gate in the pASIC macro cell is described here once. 2. Logical section—the logical ..  Tags: and logic gate pdf single gate logic  logic gate or  logic gate and  logic gate   datasheet abstract..	24.79 Kb	4 Pages	Original
	First line: EL7243 Data Sheet January 1996, FN7286 Dual Input, High Speed, Dual Channel Driver Abstract: .. R8 21 22 100 C2 25 1 43.3pF D2 24 23 dmod X3 23 21 3 1 comp1 X4 26 25 22 1 comp1 X5 16 26 17 1 And-gate sp 10 8 17 1 spmod sn 8 1 17 1 snmod g1 11 1 13 1 938u 938u g2 21 1 23 1 938u 938u .model dmod d .model spmod vswitch ron=3 roff ..  Tags:   EL7243 FN7286	102.44 Kb	7 Pages	Original
	First line: Plastic Packages Integrated Circuits Small Outline Plastic Packages (SSOP) INDEX AREA SEATING PLANE 0.25 0.010 GAUGE PLANE 0.25(0.010) M16.209 (JEDEC MO-150-AC ISSUE LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.20mm 20mm 0.0078 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall ..  Tags:   MO-150-AC	91.41 Kb	1 Pages	Original
	First line: MO-150-AE Plastic Packages Integrated Circuits Shrink Small Outline Plastic Packages (SSOP) INDEX AREA 0.25 0.010 GAUGE PLANE 0.25(0.010) M20.209 (JEDEC MO-150-AE ISSUE LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.20mm 20mm 0.0078 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. In-terlead flash and protrusions shall ..  Tags: MO-150-AE   MO-150-AE	38.26 Kb	1 Pages	Original
	First line: INDEX AREA SEATING PLANE 0.25(0.010) M18.3 (JEDEC MS-013-AB ISSUE LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.15mm 15mm 0.006 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall ..  Tags:   MS-013-AB	92.19 Kb	1 Pages	Original
	First line: M14.15 (JEDEC MS-012-AB ISSUE LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.15mm 15mm 0.006 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall ..  Tags: m14 transistor   MS-012-AB	38.82 Kb	1 Pages	Original
	First line: Plastic Packages Integrated Circuits Shrink Small Outline Plastic Packages (SSOP) INDEX AREA SEATING PLANE 0.25 0.010 GAUGE PLANE 0.25(0.010) M28.209 (JEDEC MO-150-AH ISSUE LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.20mm 20mm 0.0078 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall ..  Tags:   MO-150-AH	91.78 Kb	1 Pages	Original
	First line: Plastic Packages Integrated Circuits Shrink Small Outline Plastic Packages (SSOP) INDEX AREA SEATING PLANE 0.25 0.010 GAUGE PLANE 0.25(0.010) M24.209 (JEDEC MO-150-AG ISSUE LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL 0.002 0.065 0.009 0.004 0.312 0.197 0.072 0.014 0.009 0.334 0.220 0.078 Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.20mm 20mm 0.0078 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter-lead flash and protrusions shall ..  Tags:   MO-150-AG	11.89 Kb	1 Pages	Original
	First line: INDEX AREA SEATING PLANE 0.25(0.010) M24.3 (JEDEC MS-013-AD ISSUE LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.15mm 15mm 0.006 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter-lead flash and protrusions shall ..  Tags:   MS-013-AD	91.82 Kb	1 Pages	Original
	First line: INDEX AREA SEATING PLANE 0.25(0.010) M20.3 (JEDEC MS-013-AC ISSUE LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.15mm 15mm 0.006 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall ..  Tags: PCL86  MS-013-AC   MS-013-AC	90.84 Kb	1 Pages	Original
	First line: INDEX AREA SEATING PLANE 0.25(0.010) M16.3 (JEDEC MS-013-AA ISSUE LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.15mm 15mm 0.006 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall ..  Tags:   MS-013-AA	92.04 Kb	1 Pages	Original
	First line: M28.3 (JEDEC MS-013-AE ISSUE LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.15mm 15mm 0.006 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. In-terlead flash and protrusions shall ..  Tags:   MS-013-AE	11.74 Kb	1 Pages	Original
	First line: jedec MS-012-AC INDEX AREA SEATING PLANE 0.25(0.010) M16.15 (JEDEC MS-012-AC ISSUE LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL Abstract: .. Mold flash, protrusion and gate burrs shall not exceed 0.15mm 15mm 0.006 inch per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall ..  Tags: jedec MS-012-AC   MS-012-AC	91.8 Kb	1 Pages	Original
	First line: national semiconductor databook 54AC08 Quad 2-Input Gate 54AC08 Quad 2-Input Gate Abstract: .. 54AC08 54AC08 Quad 2-Input AND Gate General Description The ’AC08 AC08 contains four, 2-input AND gates. Features n ICC reduced by 50% n Outputs source/sink 24 mA. n Standard Microcircuit Drawing SMD 5962 ..  Tags: national semiconductor databook   54AC08	117.99 Kb	5 Pages	Original
	First line: DM54LS15 DM74LS15 Triple 3-Input Gate with Open-Collector Outputs 1992 DM54LS15 DM74LS15 Triple 3-Input Gate with Open-Collector Outputs Abstract: .. TL/F/10167. DM54LS15 DM54LS15 /DM74LS15 DM74LS15 Triple 3-Input AND Gate with Open-Collector Outputs. May 1992. DM54LS15 DM54LS15 /DM74LS15 DM74LS15 Triple 3-Input AND Gate with Open-Collector Outputs. General Description This ..  Tags: DM74LS15N  "C1995 National Semiconductor" "DM74"   DM54LS15 DM74LS15	113.03 Kb	6 Pages	Original
	First line: DIP14 package HEF4081BT HEF4081B Quad 2-input gate Rev. 2008 Product data sheet Abstract: .. The HEF4081B HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD ..  Tags: HEF4081BT DATA SHEET.PDF  hef4081bp  HEF4081B  DIP14 package HEF4081BT   HEF4081B	63.29 Kb	11 Pages	Original
	First line: 1/"AND Gate"� NC7WZ08 TinyLogic® Dual 2-Input Gate NC7WZ08 TinyLogic® Dual 2-Input Gate Abstract: .. UHS Dual 2-Input AND Gate. �2000 Fairchild Semiconductor Corporation www.fairchildsemi.com. NC7WZ08 NC7WZ08 Rev. 1.11.0. October 2008. NC7WZ08 NC7WZ08 TinyLogic. �. UHS Dual 2-Input AND Gate. Features. ■. Space saving ..  Tags: 1/"AND Gate"Â   NC7WZ08	610.23 Kb	10 Pages	Original
	First line: SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS283C JANUARY 1993 REVISED SEPTEMBER 1996 EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Protection Exceeds 2000 MIL-STD-883, Method 3015; Exceeds Using Machine Model Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Out Abstract: .. QUADRUPLE 2-INPUT POSITIVE-AND GATE. SCAS283C SCAS283C ‐ JANUARY 1993 ‐ REVISED SEPTEMBER 1996. 1 POST OFFICE BOX 655303 ∞ DALLAS, TEXAS 75265. EPICΕ Enhanced-Performance Implanted CMOS Submicron Process ..  Tags:   SN74LVC08A	99.44 Kb	5 Pages	Original
	First line: SN74AHC1G08 SINGLE 2-INPUT POSITIVE-AND GATE SCLS314A MARCH 1996 REVISED 1996 Operating Range: 5.5-V EPIC (Enhanced-Performance Implanted CMOS) Process High Latch-Up Immunity Exceeds JEDEC Standard JESD-17 Packaged Plastic Small-Outline Transistor Package Abstract: .. SINGLE 2-INPUT POSITIVE-AND GATE. SCLS314A SCLS314A ‐ MARCH 1996 ‐ REVISED MAY 1996. 1 POST OFFICE BOX 655303 ∞ DALLAS, TEXAS 75265. Operating Range: 2-V to 5.5-V VCC EPICΕ Enhanced-Performance Implanted ..  Tags:   SN74AHC1G08	99 Kb	5 Pages	Original
	First line: 74AC08, 74ACT08 Quad 2-Input Gate 74AC08, 74ACT08 Quad 2-Input Gate Abstract: .. 74AC08 74AC08 , 74ACT08 74ACT08 — Quad 2-Input AND Gate. �1988 Fairchild Semiconductor Corporation www.fairchildsemi.com. 74AC08 74AC08 , 74ACT08 74ACT08 Rev. 1.5.1. January 2008. 74AC08 74AC08 , 74ACT08 74ACT08 Quad 2-Input AND Gate. Features ..  Tags: Fairchild 74act08  ACT08  74AC08  74ac fairchild   74AC08 74ACT08	292.82 Kb	10 Pages	Original
	First line: QAN2 Counter Designs pASIC Device HIGHLIGHTS Free running counters High-speed counters optimized binary counting frequencies excess MHz. Counters with added features Binary counters with LOAD data inputs, COUNT ENABLE, UP/DOWN count capability, 3-State output control, synchronous asynchronous clear Abstract: .. An AND gate control drives the S Select input of each multiplexer. When the AND gate output is HIGH, the inverting feedback path through the multiplexer is selected causing the register output ..  Tags: loadable counter with schematics and timing diagr   datasheet abstract..	142.91 Kb	16 Pages	Original
	First line: SN74LV08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE Controlled Baseline Assembly/Test Site, Fabrication Site Extended Temperature Performance -40°C 105°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree Typical VOLP (Output Gro Abstract: .. QUADRUPLE 2-INPUT POSITIVE-AND GATE. SCLS481 SCLS481 – MAY 2003. 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265. Controlled Baseline – One Assembly/Test Site, One Fabrication Site. Extended Temperature ..  Tags:   SN74LV08A-EP	109.73 Kb	7 Pages	Original
	First line: SN74AUC1G08 SINGLE 2-INPUT POSITIVE-AND GATE Available Texas Instruments NanoStar NanoFree Packages Optimized 1.8-V Operation 3.6-V Tolerant Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Operable Power Consumption, 10-µA ±8-mA Output Drive Latch-Up Abstract: .. SINGLE 2-INPUT POSITIVE-AND GATE. SCES374J SCES374J – SEPTEMBER 2001 – REVISED JUNE 2003. 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265. Available in the Texas Instruments NanoStar and NanoFree Packages ..  Tags:   SN74AUC1G08	302.1 Kb	12 Pages	Original
	First line: "XOR Gate" QAN4 Fast Accumulators There many methods designing adders accumulators. style adopted QuickLogic accumulators called conditional addition. This style adder takes advantage versatility QuickLogic logic cell, incorporates variety high-speed design techniques. .accumulators operate between Abstract: .. Notice in the boxed areas of Figure 2 that an OR2i0 and an AND2i0 are feeding an AND gate. By changing the OR to a NOR and bubbling the appropriate input of the AND gate, the QuickLogic Packer tool will ..  Tags: "XOR Gate" schematic XOR Gates   datasheet abstract..	77.33 Kb	6 Pages	Original
	First line: "AND Gate" "XOR Gate" 8 bit carry select adder 32 bit carry select adder QAN4 Fast Accumulators There many methods designing adders accumulators. style adopted QuickLogic accumulators called conditional addition. This style adder takes advantage versatility QuickLogic Logic Cell, incorporates variet Abstract: .. Notice in the boxed areas of Figure 2 that an OR2i0 and an AND2i0 are feeding an AND gate. By changing the OR to a NOR and bubbling the appropriate input of the AND gate, the QuickLogic Packer tool will ..  Tags: 8 bit carry select adder "XOR Gate" "AND Gate" schematic XOR Gates  32 bit carry select adder   datasheet abstract..	87.67 Kb	8 Pages	Original
	First line: 8 bit adder "XOR Gate" QAN4 Fast Accumulators There many methods designing adders accumulators. style adopted QuickLogic accumulators called conditional addition. This style adder takes advantage versatility QuickLogic logic cell, incorporates variety high-speed design techniques. .accumulators oper Abstract: .. Notice in the boxed areas of Figure 2 that an OR2i0 and an AND2i0 are feeding an AND gate. By changing the OR to a NOR and bubbling the appropriate input of the AND gate, the QuickLogic Packer tool will ..  Tags: "XOR Gate" schematic XOR Gates  8 bit adder   datasheet abstract..	69.24 Kb	6 Pages	Original
	First line: 74LVX08 Voltage Quad 2-Input Gate 74LVX08 Voltage Quad 2-Input Gate Abstract: .. 74LVX08 74LVX08 Low Voltage Quad 2-Input AND Gate. January 1996. 74LVX08 74LVX08 Low Voltage Quad 2-Input AND Gate. General Description The LVX08 LVX08 contains four 2-input AND gates. The inputs tol-erate voltages ..  Tags:   74LVX08	114.11 Kb	6 Pages	Original
	First line: lcx08 74LCX08 Voltage Quad 2-Input Gate with Tolerant Inputs 74LCX08 Voltage Quad 2-Input Gate with Tolerant Inputs Abstract: .. TL/F/12411. 74LCX08 74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs. November 1996. 74LCX08 74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs. General Description The LCX08 LCX08 contains ..  Tags: lcx08  74LCX08*   74LCX08	115.35 Kb	6 Pages	Original
	First line: FPGAs ASICs Shelly Davis, HardWire Marketing Manager, sdavis@xilinx.com Rapidly Changing ASIC Conversion Market programmable logic devices continue grow density, designers increasingly using FPGAs where they previously used ASICs. advantages off-the-shelf availability rapid prototyping make FPGAs ve Abstract: .. At process geometries below 0.5μ, many architectures, including FPGAs and gate arrays, become pad limited. For an FPGA-to-ASIC conversion company, who depends on achieving cost reduction ..  Tags: Gate Array   datasheet abstract..	218.68 Kb	2 Pages	Original
	First line: 1000 volt mosfet AN9209.1 Harris Power MOSFETs Abstract: .. DRAIN AND GATE VOLTAGE vs TIME DETERMINE C1, C2, C3 AND VPINCH. VTHRESHOLD VGS VOLTS 4.0 5.0 6.0 7.0. SLOPE AT KP. VDS > VGS. SATURATED REGIME √I DS. AMPERES1/2 IDS RS. RFP15N15 RFP15N15 . 0. SLOPE ≈ RD + RS. V DS ..  Tags: "HIGH Power MOSFET" ronan*  Power MOSFET Switching Waveforms A New Insight, H  p jfet  1000 volt mosfet   AN9209	68.33 Kb	4 Pages	Original
	First line: SOT-23 5 PIN MARK G10 SOT23-5 7z08* G10 sot23-5 NC7SZ08 Tiny 2-Input Gate NC7SZ08 Tiny 2-Input Gate Abstract: .. NC7SZ08 NC7SZ08 Tiny UHS 2-Input AND Gate. December 1996. NC7SZ08 NC7SZ08 Tiny UHS 2-Input AND Gate. General Description The NC7SZ08 NC7SZ08 is a single 2-Input AND Gate from National’s Ultra High Speed Series of TinyLogic ..  Tags: G10 sot23-5 7z08* MARK G10 SOT23-5 SOT-23 5 PIN a25 sot23-5  12165   NC7SZ08	131.5 Kb	8 Pages	Original
	Datasheets per page:  50 | 250 | 500

Access Notice

Unusual activity from your IP address or subnet. Our Cross reference data is temporarily hidden from view. One of our administrators will manually check this activity.

Search Syntax | Privacy Policy | Disclaimer
© 2012 Datasheet Archive